555 Timer
A functional block diagram of the 555 timer is shown in Fig. 1. Various timing functions can be obtained by connecting resistors and capacitors around the 555.
The 555 consists of two voltage comparators (C1 and C2), an R-S flip-flop FF, a discharge transistor Q14, a resistive voltage divider (R3, R4, R5), and an output buffer.
The (-) input of the voltage comparator C1 is internally connected to the resistive voltage divider. The voltage at the (-) input is equal to VH = 2VCC=3, which is called the threshold level. The (+) input of the comparator C1 is connected to the external THRESHOLD pin (pin 6). The (+) input of the voltage comparator C2 is connected to VL = VCC=3, which is called the trigger level, while the (-) input is the external TRIGGER pin (pin 2). The (-) input of the voltage comparator C1 is also available as the CONTROL pin (pin 5), which can be used for external adjustment of the threshold and trigger levels.
The comparator C1 and C2 outputs are the reset R and the set S inputs, respectively, for the flip-flop. When the TRIGGER input falls bellow the trigger level VL, the output of the voltage comparator C2 goes high and sets the flip-flop. If the TRIGGER input is above the trigger level, and the THRESHOLD input is above the threshold level, the output of the voltage comparator C1 is high and the flip-flop is reset. The flip-flop output Q drives the discharge transistor Q14, and an inverting output buffer: when the flip-flop output Q is high, Q14 is on and the voltage at the OUTPUT pin (pin 3) is low (close to zero); when the flip-flop output Q is low, Q14 is off and the OUTPUT is high (close to VCC). The output driver is capable of sinking or sourcing current up to about 200mA. The collector of the discharge transistor Q14 is available at the DISCHARGE pin (pin 7).
The active-low RESET input (pin 4) to the flip-flop can be used to disable the timer operation and ensure that the OUTPUT stays at zero, regardless of the comparator outputs.
The dc supply voltage can be between VCC = 5V and VCC = 15V. It should be connected between the VCC (pin 8) and the GROUND (pin 1). With a 5V supply, the output, and the RESET input levels are compatible with standard TTL or CMOS digital logic circuits.
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astable Operation
With the addition of an external capacitor and two external resistors, the 555 can be configured to produce a periodic pulsating waveform at the output, without any external trigger pulses. The basic configuration for the astable operation is shown in Fig. 5, together with typical steady-state waveforms in Fig. 2.
The key difference between the monostable and the astable operation is that the TRIGGER input is connected together with the THRESHOLD input so that the timer triggers itself during operation. The capacitor C is periodically charged and discharged between the trigger level VL = VCC=3 and the threshold level VH = 2VCC=3. Suppose that at t = 0 the output is high, and the discharge transistor Q14 is off. The capacitor is charged through RA and RB until the capacitor voltage reaches VH = 2VCC=3 at t = tH. At this point, the flip-flop is reset, the output goes low, and the discharge transistor Q14 is turned on. As a result, C is discharged through RB and the saturated discharge transistor Q14. At t = tH + tL = Tp, the capacitor voltage drops to VL = VCC=3, the flip-flop is set again, the output voltage goes high and the discharge transistor is turned off, starting another period.
The times tH and tL can be determined using the same approach used to determine Tw in the monostable circuit. The results are:
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The period of the waveforms is
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and the frequency is fp = 1/Tp. The output waveform duty cycle D is:
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Since tH > tL, the duty cycle must be greater than 50% in this configuration.
